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SST823 SST824
Linear Integrated Systems
FEATURES HIGH SWITCHING SPEED LOW ON RESISTANCE LOW GATE NODE CAPACITANCE LOW GATE LEAKAGE CAPACITANCE ABSOLUTE MAXIMUM RATINGS1 @ 25 C (unless otherwise stated) Maximum Temperatures Storage Temperature Operating Junction Temperature Maximum Power Dissipation Continuous Power Dissipation Maximum Currents Pulsed Drain Current3 Continuous Drain Current2 Maximum Voltages VDSO VSDO VDB Drain to Source Source to Drain Drain to Body SST823 SST824 SST823 SST824 +25V +15V +20V +22.5V +30V VSB VGB VGS VGD Source to Body Gate to Body Gate to Source Gate to Drain SST823 SST824 +22.5V +25V +30V 22.5V 22.5V IDS = 1A IDS = 200mA
2
HIGH SPEED N-CHANNEL LATERAL DMOS SWITCH ZENER PROTECTED
tON = 2.0ns rDS(ON) = 5 C = 25pF IG(ON) = 0.05A
1. Body 2. Source
-55 to +150 C -55 to +125 C PD = 300mW
3. Drain
4. Gate
ELECTRICAL CHARACTERISTICS @ 25 C (unless otherwise stated) SYMBOL BVDS BVSD BVDB BVSB VGS(OFF) rDS(ON) gfs ID(OFF) IS(OFF) IG(OFF) IG(ON) CHARACTERISTIC Breakdown Voltage Drain to Source Breakdown Voltage Source to Drain Breakdown Voltage Drain to Body Breakdown Voltage Source to Body Cutoff Voltage Gate to Source On Resistance Drain to Source4 Forward Transconductance
4
MIN 25 15 SST823 SST824 SST823 SST824 SST823 SST824 15 20 22.5 25 22.5 25 0.1
TYP
MAX UNITS CONDITIONS V V V V 2 7.5 5.0 V mmho 100 100 100 10 nA nA nA A ID = 10A, VGS = VBS = 0 ID = 100nA, VGS = VBS = -5V IS = 100nA, VGD = VBD = -5V ID = 100nA, VGB = 0, Source Open IS = 100nA, VGB = 0, Drain Open VDS = VGS, VSB = 0V, ID = 10A VGS = 5.0V, ID = 50mA, VSB = 0 VGS = 10V, ID = 500mA, VSB = 0 VDS = 15V, ID = 200mA VGS = VBS = -5V, VDS = 15V VGD = VBD = -5V, VDS = 15V VGB = 0V, VGS = VGD = -22.5V VGB = 30V, VGS = VGD = 22.5V
100
120
Leakage Current Drain Node Leakage Current Source Node Leakage Current Gate Node (OFF) Leakage Current Gate Node (ON)
Linear Integrated Systems
* 4042 Clipper Court * Fremont, CA 94538 * Tel: 510 490-9160 * Fax: 510 353-0261
ELECTRICAL CHARACTERISTICS CONT. SYMBOL C(GS+GD+GB) C(GD+DB) C(GS+SB) CDG tON tOFF CHARACTERISTIC Capacitance Gate Node Capacitance Drain Node Capacitance Source Node Capacitance Reverse Transfer Turn On Time
5
MIN
TYP 25 13 35 3 2.0 3.0
MAX UNITS CONDITIONS 30 15 40 5 3.0 4.0 pF pF pF pF ns ns VDD = 10V, VG(ON) = 10V, RL = 133, RG = 51 VDS = 10V, VGS = VBS = -15V, f = 1MHz
Turn Off Time5
SWITCHING CHARACTERISTICS VGG VDD 5V 5V 10V 20V 5V 10V 10V 20V RL 100 200 300 67 133 270 td(ON) TYP <1ns <1ns <1ns <1ns <1ns <1ns tr TYP 1ns 1ns 1ns 1ns 1ns 1ns tOFF TYP 3ns 3ns 3ns 3ns 3ns 3ns
TEST CIRCUIT INPUT PULSE td, tr < 1ns Pulse Width = 10ns Rep Rate = 1MHz SAMPLING SCOPE tr < 360 ps RIN = 1M CIN = 2.0pF
VIN 51 TO SCOPE VDD
510
RL VOUT TO SCOPE
VGG
PACKAGE OPTION
TO-72 PIN LAYOUT
SWITCHING WAVEFORMS
VGG VIN 0V + VDD VOUT 0V
90% 50% 10%
td(on)
90% 50% 10%
tr
tOFF
DRIVER / SWITCH APPLICATION
15V Analog Output 7.5V
1 k Driver SST211 15V VC 1 k VC 0 5V -15V
Switch SST823
RB* RB* Optional Current Limiting Resistor
Analog Input 7.5V -15V
NOTES
1. 2. 3. 4. 5. Absolute maximum ratings are limiting values above which serviceability may be impaired. For SOT143 package only. Pulsed @ 80 s, 1% duty cycle. See test conditions in Electrical Characteristics section. See Switching Characteristics and Test Circuit for detail.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
Linear Integrated Systems
* 4042 Clipper Court * Fremont, CA 94538 * Tel: 510 490-9160 * Fax: 510 353-0261

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